// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  vpc_top_nmanager_reg_offset.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2013/3/10
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/19 14:40:32 Create file
// ******************************************************************************

#ifndef __VPC_TOP_NMANAGER_REG_OFFSET_H__
#define __VPC_TOP_NMANAGER_REG_OFFSET_H__

/* VPC_TOP_NMANAGER Base address of Module's Register */
#define SOC_VPC_TOP_NMANAGER_BASE                       (0x13000)

/******************************************************************************/
/*                      SOC VPC_TOP_NMANAGER Registers' Definitions                            */
/******************************************************************************/

#define SOC_VPC_TOP_NMANAGER_VPC_CONTROL_1_REG           (SOC_VPC_TOP_NMANAGER_BASE + 0x0)  /* VPC start control */
#define SOC_VPC_TOP_NMANAGER_VPC_CONTROL_2_REG           (SOC_VPC_TOP_NMANAGER_BASE + 0x4)  /* VPC top configuration */
#define SOC_VPC_TOP_NMANAGER_VPC_CONTROL_3_REG           (SOC_VPC_TOP_NMANAGER_BASE + 0x8)  /* VPC clock gate control */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_HADDR1_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0xC)  /* RDMA head address 1 */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_HADDR2_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x10) /* RDMA head address 2 */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_HSTRIDE_REG        (SOC_VPC_TOP_NMANAGER_BASE + 0x14) /* RDMA head stride */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_PADDR1_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x18) /* RDMA payload address 1 */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_PADDR2_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x1C) /* RDMA payload address 2 */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_PSTRIDE_REG        (SOC_VPC_TOP_NMANAGER_BASE + 0x20) /* RDMA payload stride */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_PIC_SIZE_REG       (SOC_VPC_TOP_NMANAGER_BASE + 0x24) /* VPC RDMA input picture size */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_STATUS1_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x28) /* VPC original normal interrupt status 1 */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_STATUS2_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x2C) /* VPC original normal interrupt status 2 */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_MASK1_REG           (SOC_VPC_TOP_NMANAGER_BASE + 0x30) /* VPC normal interrupt mask 1 */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_MASK2_REG           (SOC_VPC_TOP_NMANAGER_BASE + 0x34) /* VPC normal interrupt mask 2 */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_MASK_STATUS1_REG    (SOC_VPC_TOP_NMANAGER_BASE + 0x38) /* VPC normal interrupt status 1 after mask */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_MASK_STATUS2_REG    (SOC_VPC_TOP_NMANAGER_BASE + 0x3C) /* VPC normal interrupt status 2 after mask */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_CLR1_REG            (SOC_VPC_TOP_NMANAGER_BASE + 0x40) /* VPC normal interrupt status 1 clear */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_CLR2_REG            (SOC_VPC_TOP_NMANAGER_BASE + 0x44) /* VPC normal interrupt status 2 clear */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_SET1_REG            (SOC_VPC_TOP_NMANAGER_BASE + 0x48) /* VPC normal interrupt status 1 set */
#define SOC_VPC_TOP_NMANAGER_VPC_INT_SET2_REG            (SOC_VPC_TOP_NMANAGER_BASE + 0x4C) /* VPC normal interrupt status 2 set */
#define SOC_VPC_TOP_NMANAGER_EOF_INT1_MERGE_ENABLE_REG   (SOC_VPC_TOP_NMANAGER_BASE + 0x50) /* interrupt 'vpc_eof_in1' merged source enable */
#define SOC_VPC_TOP_NMANAGER_EOF_INT2_MERGE_ENABLE_REG   (SOC_VPC_TOP_NMANAGER_BASE + 0x54) /* interrupt 'vpc_eof_in2' merged source enable */
#define SOC_VPC_TOP_NMANAGER_CMDLIST_IN_INT_CTRL_REG     (SOC_VPC_TOP_NMANAGER_BASE + 0x58) /* command list input interrupt control */
#define SOC_VPC_TOP_NMANAGER_VPC_ERR_INT_STATUS_REG      (SOC_VPC_TOP_NMANAGER_BASE + 0x5C) /* VPC original error interrupt status */
#define SOC_VPC_TOP_NMANAGER_VPC_ERR_INT_MASK_REG        (SOC_VPC_TOP_NMANAGER_BASE + 0x60) /* VPC error interrupt mask */
#define SOC_VPC_TOP_NMANAGER_VPC_ERR_INT_MASK_STATUS_REG (SOC_VPC_TOP_NMANAGER_BASE + 0x64) /* VPC error interrupt status after mask */
#define SOC_VPC_TOP_NMANAGER_VPC_ERR_INT_CLR_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x68) /* VPC error interrupt status clear */
#define SOC_VPC_TOP_NMANAGER_VPC_ERR_INT_SET_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x6C) /* VPC error interrupt status set */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_1_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x70) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_2_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x74) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_3_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x78) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_4_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x7C) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_5_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x80) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_6_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x84) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_7_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x88) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_8_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x8C) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_9_REG          (SOC_VPC_TOP_NMANAGER_BASE + 0x90) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_BUS_CTRL_10_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0x94) /* VPC AXI Bus control */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_DEBUG_1_REG        (SOC_VPC_TOP_NMANAGER_BASE + 0x98) /* VPC RDMA HFDCD fifo status output */
#define SOC_VPC_TOP_NMANAGER_VPC_RDMA_DEBUG_2_REG        (SOC_VPC_TOP_NMANAGER_BASE + 0x9C) /* VPC RDMA error information */
#define SOC_VPC_TOP_NMANAGER_VPC_LINEBUF_DEBUG_1_REG     (SOC_VPC_TOP_NMANAGER_BASE + 0xA0) /* VPC line buffer debug information */
#define SOC_VPC_TOP_NMANAGER_VPC_LINEBUF_DEBUG_2_REG     (SOC_VPC_TOP_NMANAGER_BASE + 0xA4) /* VPC line buffer debug information */
#define SOC_VPC_TOP_NMANAGER_VPC_LINEBUF_DEBUG_3_REG     (SOC_VPC_TOP_NMANAGER_BASE + 0xA8) /* VPC line buffer debug information */
#define SOC_VPC_TOP_NMANAGER_VPC_LINEBUF_DEBUG_4_REG     (SOC_VPC_TOP_NMANAGER_BASE + 0xAC) /* VPC line buffer debug information */
#define SOC_VPC_TOP_NMANAGER_VPC_CMDLST_DEBUG_REG        (SOC_VPC_TOP_NMANAGER_BASE + 0xB0) /* VPC command list debug information */
#define SOC_VPC_TOP_NMANAGER_VPC_SP_RAM_CTRL_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0xB4) /* vpc spram control */
#define SOC_VPC_TOP_NMANAGER_VPC_TP_RAM_CTRL_REG         (SOC_VPC_TOP_NMANAGER_BASE + 0xB8) /* vpc tpram control */

#endif // __VPC_TOP_NMANAGER_REG_OFFSET_H__
